This invention relates to semiconductor devices, and more particularly to sense amplifier circuits of the type used in CMOS semiconductor memory devices.
Semiconductor dynamic read/write memory devices such as the 16K DRAM of U.S. Pat. No. 4,071,801, or the 64K DRAM of U.S. Pat. No. 4,239,993, have been manufactured using NMOS processing as set forth in U.S. Pat. Nos. 4,055,444 and 4,242,092, for example; said patents being assigned to Texas Instruments. It is preferable to employ CMOS processing, however, when low power dissipation is a primary objective. The sense amplifiers consume a significant part of the total power in a dynamic RAM, and so it is preferable that the sense amplifier chosen is a CMOS circuit. Previous CMOS sense amplifiers have been either two large or have been unbalanced when laid out for manufacture in a semiconductor bar. The sense amplifier must lay out in such a manner that it fits within the pitch of bit lines of the cell array, placing one constraint upon the design. Of course, the components should be electrically and physically balanced to avoid introducing differential voltage or capacitance at the sense nodes.
It is the principal object of this invention to provide improved sense amplifier circuits for semiconductor memory devices, particularly devices made by CMOS processing. Another object is to provide improved sense amplifier circuits which can be constructed in CMOS technology in a balanced configuration.